Staff Engineer, Design Verification Engineering
Core
Architecting and designing key digital blocks in SoC designs, optimizing micro-architecture for power, performance, and area tradeoffs, and leading design verification activities.
Role type
Staff Engineer, Design Verification Engineering
Builds
ASIC tapeouts (not FPGA) for SoC designs
Domain
Semiconductor, Analog/Digital/AI, SoC architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital logic design, SoC/Processor architecture, Power-performance-area optimization, Lint, CDC, formal equivalence, ECO flows, scripting, Post Silicon debug, DSP fundamentals
Preferred skills
Technical leadership, mentoring junior engineers, cross-functional product development collaboration
Technologies
Lint, CDC, formal equivalence, ECO flows, scripting
Responsibilities
Architecting and designing key digital blocks in SoC designs, analyzing power/performance/area tradeoffs, leading design verification activities, participating in post-silicon issue debug, technically mentoring junior engineers
Seniority
Staff, hands-on IC with technical leadership
