Senior Verification Engineer
Core
Own verification efforts for complex security IP and subsystem designs, ensuring robust functionality and security across hardware solutions.
Role type
Senior IC design verification engineer (hardware security)
Builds
Next-generation hardware security solutions integrating embedded processors, cryptographic accelerators, and secure memory architectures
Domain
Semiconductor / Hardware Security
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random verification, functional coverage, assertion-based verification (SVA), regression management, RTL simulation/debug, Python/Perl/Tcl scripting, SoC verification, C test case development, embedded processor verification (ARM/RISC-V), SoC interface knowledge (APB/AXI/DMA)
Preferred skills
Hardware security IP verification (AES/SHA/RSA/ECC), secure enclave architectures, formal verification, emulation platforms, AI-assisted engineering tools
Technologies
VCS, Xcelium, Simvision, Verdi, Questa, SystemVerilog, UVM, Python, Perl, Tcl, ARM Cortex-M, RISC-V, APB, AHB, AXI, QSPI, UART, DMA
Responsibilities
Develop comprehensive verification plans based on architecture specifications and threat models; Create and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, and coverage models; Drive verification closure through code, functional, and assertion coverage analysis; Debug complex RTL and simulation failures and perform root-cause analysis; Collaborate with design, architecture, and firmware teams to understand design intent; Mentor junior verification engineers on best practices
Seniority
Senior, hands-on IC
