Principal Digital Design Engineer (ASIC)
Core
Drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs), defining roadmaps and leading ASIC architecture for mission-critical projects.
Role type
Principal Digital Design Engineer (ASIC/SoC)
Builds
Mixed signal ICs with complex digital blocks and subsystems (signal processing, control, processor subsystems)
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog), logic synthesis, digital verification methodologies, timing analysis and constraints, design automation scripting (Matlab, TCL, Python), system-level modeling, silicon lab evaluation and debug
Preferred skills
High-speed interface design, low-power design, UVM verification frameworks, technical leadership and mentorship
Technologies
SystemVerilog, MATLAB, Cadence tools, Python, TCL, UVM
Responsibilities
Develop system-level models to analyze architectural trade-offs and verify system behavior; Own architecture, micro-architecture, and RTL design of complex digital blocks; Perform RTL coding, synthesis, and lint/CDC analysis to drive timing closure; Lead design reviews and ensure alignment with project goals; Mentor junior engineers and promote best practices; Author and maintain clear documentation and design collateral.
Seniority
Principal, strategy & mentorship
