Digital Mixed Signal (DMS) Design Verification Engineer
Core
Design verification of highly integrated analog/mixed-signal products using behavioral modeling and digital RTL/PA/Gates.
Role type
Senior IC design verification engineer (DMS)
Builds
Next generation Intelligence at the Edge products
Domain
Semiconductor, Mixed-Signal/Analog/Digital
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal behavioral modeling, UVM/SV, Cadence Virtuoso, Cadence Xcelium/Synopsys VCS, Python/Perl/Shell scripting, C, Metric Driven Verification (MDV)
Preferred skills
RF design architectures, Schematic capture tools, Waveform viewers, Self-checking testcases, Regression management
Technologies
UVM, SV, Cadence Virtuoso, Cadence Simvision, Cadence Xcelium, Synopsys VCS, vManager
Responsibilities
Develop verification strategy and plans for mixed-signal products, Create analog/mixed-signal models for chip-top verification, Build verification environments and self-checking testcases, Collaborate with system architects and digital/analog design teams for first pass silicon, Support post-silicon validation with test and characterization teams, Deploy innovative verification methodologies to reduce time-to-market
Seniority
Senior, hands-on IC