Senior Analog Layout Engineer
Core
Design high-precision analog integrated circuits from block to top-level, ensuring physical verification and performance optimization.
Role type
Senior IC analog layout engineer
Builds
High-precision analog chips (DAC, ADC, LDO, Bandgap, AMP)
Domain
Semiconductor / Analog IC design
Required skills
top-down physical design, full-chip/block level layout, place and route, floor planning, power and clock optimization, noise isolation, DFM compliant layouts, physical verifications, device matching, layout dependent effects, shielding, EM/IR drop analysis, ESD/Latch up, device isolation, circuit theory for high-precision analog
Preferred skills
tape out flow expertise, IC package design knowledge, cross-site team collaboration
Technologies
DRC, LVS, Antenna check tools, foundry process tools
Responsibilities
Perform block to top-level layout design including floor plan, package implementation and top-level integration; Perform DRC, LVS, Antenna and other physical verifications to sign off project tape out; Use physical layout knowledge to improve project performance; Manage layout schedules and resource allocation
Seniority
Senior, hands-on IC design with mentorship
