Staff Engineer, Design Verification Engineering
Core
Lead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure for next-generation Intelligence at the Edge products.
Role type
Staff Engineer, Digital Design Verification
Builds
Highly integrated solutions and products across multiple business units
Domain
Semiconductor / SoC Design / Digital Verification
Deliverable
production ML models | product features
Required skills
SoC/subsystem architecture, Verilog/SystemVerilog, UVM, functional and code coverage, NoC/interconnect verification, formal verification, power-aware verification (UPF), constrained-random verification, transaction-level modeling, C/C++, Python/TCL/Shell
Preferred skills
Processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures, gate-level simulation (GLS)
Technologies
UVM, SystemVerilog, UPF, Python, TCL, Shell, ARM, RISC-V, Tensilica
Responsibilities
Lead pre-silicon verification for complex SoC or subsystem designs; Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals; Architect and implement UVM-based testbenches and DV flows; Define and execute test plans for functional and code coverage closure; Work cross-functionally with emulation, FPGA, and firmware teams; Apply formal verification techniques for IP and subsystem-level validation; Lead NoC/interconnect verification; Perform system-level use case validation including performance analysis.
Seniority
Staff, hands-on IC with strategic influence
