Analog Layout Engineer
Core
Senior Analog Layout Engineer responsible for full-chip and large-scale analog/mixed-signal layout ownership from floorplan through tapeout, ensuring signoff closure and performance targets in harsh industrial environments.
Role type
Senior IC analog layout engineer (mixed-signal)
Builds
Large silicon systems for industrial automation, communication, and measurement/control
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: physical/clinical work -> infrastructure/physical work context, but strictly following schema: physical/clinical work is not right. Let's re-evaluate deliverable. It's building silicon chips. The schema options are: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work. None fit 'silicon chips' perfectly, but 'product features' (the chip itself) or 'infrastructure' (the physical layer) are closest. However, looking at the list, 'product features' usually implies software. 'Infrastructure' implies backend systems. This is hardware. Let's look at the options again. Actually, the prompt says 'one of: ...'. If none fit, I must choose the closest or omit? The instruction says 'Omit a label entirely when nothing is stated'. But 'Deliverable' is a required label in the list. Let's assume 'product features' covers the physical product or 'infrastructure' covers the physical substrate. Given the context of 'silicon solutions', 'product features' is the most logical fit for the chip as a product component. Wait, the schema options are fixed. Let's pick 'product features' as the chip is the product feature being built.
Required skills
Full-custom IC layout, analog/mixed-signal design, floorplanning, physical verification (DRC/LVS/ERC), parasitic extraction, EM/IR analysis, ESD-aware layout, matching techniques, noise isolation, substrate/well strategy, scripting/automation (SKILL/PERL)
Preferred skills
Top-level integration of mixed-signal chips, advanced CMOS nodes, Analog-on-Top (AoT) and Digital-on-Top (DoT) flows, high-voltage layout, BiCMOS technologies, PCELL creation, methodology improvement
Technologies
Custom layout tools, verification/signoff flows, SKILL, PERL, AMPLE
Responsibilities
Layout ownership for full-chip and large-scale analog/mixed-signal blocks, floorplan development at block/subsystem/full-chip levels, top-level integration of mixed-signal chips, schedule and milestone ownership, physical verification leadership, parasitic extraction coordination, reliability and robustness closure, cross-functional partnership with design/verification/packaging teams, methodology improvement, technical leadership and mentoring
Seniority
Senior, hands-on IC with technical leadership
