Staff Digital Verification Engineer
Core
Design and verify digital blocks and subsystems for semiconductor products, optimizing micro-architecture for power, performance, and area goals.
Role type
Staff Digital Verification Engineer (Block/Subsystem Design & Verification)
Builds
Digital blocks, subsystems, and full-chip integrations for semiconductor solutions
Domain
Semiconductor / Digital Logic Design / Hardware Verification
Deliverable
production ML models | product features | infrastructure
Required skills
RTL coding (Verilog/System Verilog), micro-architecture optimization, timing constraint development, synthesis, LEC, digital logic design principles, bus protocols (AHB/APB/AXI), silicon validation, DFT support
Preferred skills
Digital signal processing, Matlab modeling, processor subsystem design, mentoring junior engineers
Technologies
Verilog, System Verilog, Lint, CDC, Synthesis tools, LEC, Matlab
Responsibilities
Develop block/subsystem specifications, translate specs to micro-architecture, perform block-level verification, create test plans, handle front-end implementation (linting, timing), support silicon validation and debugging
Seniority
Senior, hands-on IC with mentorship responsibilities
