Senior Staff Engineer
Core
Design Verification Engineer responsible for independent ownership of IP Design Verification (DV), creating test plans, building testbenches, and developing DV infrastructure.
Role type
Senior Staff Design Verification Engineer
Builds
Verified IP blocks, subsystems, and SoCs for System LSI, Memory, and Foundry solutions
Domain
Semiconductor Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, CDV, MDV, SoC architecture understanding, AXI, PCIe, UCIe protocol expertise, testbench development, regression/simulation scripting
Preferred skills
Hybrid testbenches (SV, SystemC, Python), SystemC reference models, team leadership, debugging
Technologies
UVM, System Verilog, SystemC, Python, AXI, PCIe, UCIe
Responsibilities
Create test plans, build testbenches based on standard DV methodology, develop DV infrastructure (coverage/regression/simulation scripts), debug verification issues, provide technical guidance to teams
Seniority
Senior Staff, hands-on IC with team leadership
