Library Design Engineer
Core
Design and optimize standard cell libraries and physical design blocks to improve Power, Performance, and Area (PPA) for semiconductor IP.
Role type
Senior IC physical design engineer (library development)
Builds
Standard cell libraries, PNR blocks, and testchip IPs for System LSI, Memory, and Foundry products.
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Library architecture design, layout optimization, parasitic reduction, standard cell circuit development, library characterization (timing/power/variation), PNR block validation, cross-functional collaboration with CPU/SOC/GPU teams
Preferred skills
Experience with multiple technology nodes and PDK releases
Technologies
PDK, testchips, PNR blocks
Responsibilities
Discuss and optimize library architecture to improve PPA, drive layout optimization to reduce parasitics, develop standard cell circuits, characterize libraries for timing/power/variation, validate IP in testchips, engage with CPU/SOC/GPU teams on physical design requirements
Seniority
Senior, hands-on IC