Design Verification Engineer, Memory Controller
Core
Verify memory controller IPs for high-performance, low-latency SoC designs, ensuring functional correctness and performance.
Role type
Senior IC design verification engineer (memory controller)
Builds
Reusable verification environments, testbenches, and validation for Samsung's custom memory controller IP
Domain
Semiconductor / Memory Subsystems / SoC Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and IP validation
Required skills
SystemVerilog, UVM, testbench architecture, coverage analysis, debugging, LPDDR memory controllers, DDR/LPDDR/HBM protocols, ARM protocols (CHI, AXI, ACElite, APB), Git, Unix/Perl scripting
Preferred skills
Formal verification, power-aware verification (UPF), gate-level simulation, cache verification, coherent interconnects
Technologies
SystemVerilog, UVM, Git, UPF
Responsibilities
Develop and maintain reusable verification environments and testbenches from scratch; execute verification strategy for memory controller IPs; debug functional failures and perform coverage analysis; collaborate with design and SoC teams to resolve spec issues and enable bring-up; define new verification methodologies and improve flows.
Seniority
Senior, hands-on IC
