SOC DV Emulation Engineer
Core
Building and delivering emulation models from scratch for System-on-Chips (SOCs) to validate hardware designs before silicon fabrication.
Role type
Senior Digital Verification Emulation Engineer
Builds
Emulation models for high-performance SoCs (Mobile SoCs, Storage Solutions, AI/ML, 5G/6G)
Domain
Semiconductor R&D, Digital Verification, Hardware Emulation
Deliverable
production ML models
Required skills
Zebu Emulator, Verilog, System Verilog, C/C++, waveform debugging (Verdi, Trace32), Transactor integration, High-Speed IP protocols (PCIe, Ethernet, CSI, UFS, CAN), LPDDR5/HBM3/PCIE/UFS/CSI/UCIE architecture knowledge
Preferred skills
Palladium experience, ARM-based SOC architecture, DV Acceleration techniques, scripting, UART/SPI/I2C protocols
Technologies
Zebu, Verdi, Trace32, PCIe, Ethernet, CSI, UFS, CAN, LPDDR5, HBM3
Responsibilities
Build emulation models from scratch for SOCs; Integrate various Transactors and AVIPS; Create test benches using Verilog/System Verilog/C++; Debug waveforms using Verdi and Trace32; Validate High-Speed IPs integration
Seniority
Mid-Senior, hands-on IC
