SOC Design Verification Engineer
Core
Developing and executing verification strategies for System-on-Chip (SoC) and IP blocks, ensuring functional coverage and sign-off from test plan development to gate-level simulation.
Role type
SOC Design Verification Engineer
Builds
Production-ready SoC designs and IP blocks for mobile, storage, and AI/ML applications
Domain
Semiconductor / System-on-Chip (SoC) / Digital Logic Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, OVM, AMBA standards (AXI, AHB, APB), Coverage-driven constrained random validation, Test bench development, Debugging, Scripting, SVA
Preferred skills
Memory protocols (HBM2/HBM3, LPDDR4~5x, GDDRx), High-speed protocols (PCIe, Ethernet, SerDes)
Technologies
UVM, System Verilog, OVM, AXI, AHB, APB, HBM2, HBM3, LPDDR4, LPDDR5, GDDR, PCIe, Ethernet, SerDes
Responsibilities
Develop test benches from scratch using UVM components; Create efficient test plans for RTL and gate-level simulations; Execute continuous regression runs and manage failure closure; Perform complex failure debug in collaboration with design teams; Achieve code, toggle, and functional coverage sign-off.
Seniority
Mid-Senior, hands-on IC
