Digital Verification Engineer Prime (FEC)
Core
Senior Digital Verification Engineer responsible for simulating and validating functional blocks and subsystems for Ciena's Forward Error Correction (FEC) IP.
Role type
Senior IC digital verification engineer
Builds
Ciena's Wavelogic modem family of products (FEC IP)
Domain
Telecommunications / High-speed connectivity / Digital verification
Deliverable
production ML models | product features
Required skills
C/C++, System Verilog, UVM, SVA, formal verification, coverage-driven verification, testbench development, regression monitoring, debugging
Preferred skills
Python, Make, bash, object-oriented programming, Jira, GIT, team leadership, mentoring
Technologies
System Verilog, UVM, C++, Python, Jira, GIT
Responsibilities
Develop verification, functional coverage, and formal verification test plans; validate architectural FEC functional blocks using simulation, formal, and coverage methods; create testbench environments, agents, scoreboards, and test scenarios; monitor regressions and debug failures; mentor and supervise junior verification engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
