FPGA IP Design and Verification Engineer
Core
Performs functional logic verification of FPGA designs to ensure they meet microarchitecture specifications and uncover bugs before silicon.
Role type
Senior IC FPGA verification engineer
Builds
Verified FPGA IP blocks and system simulation models
Domain
Semiconductor / FPGA design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production ML models is wrong, should be: production ML models is not applicable. Correcting:
Deliverable
production ML models is a fixed option in the prompt instructions? No, the prompt says 'one of: ...'. Let's re-read the prompt options: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. FPGA verification is best mapped to 'product features' (the verified IP) or 'infrastructure' (verification environment). Given the context of 'design will meet specification', 'product features' is the most accurate fit for the IP being verified. However, the role also builds the 'verification environment'. Let's choose 'product features' as the primary deliverable of the role's output (the verified design).
Required skills
Functional logic verification, HDL languages (VHDL, Verilog, SystemVerilog), Scripting (Tcl, Perl, Python), FPGA tools (Quartus, Vivado), Bug debugging, Verification planning, Technical documentation
Preferred skills
Experience with gate-level simulation, Power-aware simulation, Collaboration with RTL and physical design teams
Responsibilities
Develop FPGA verification plans, test benches, and verification environments; Execute verification plans and run system simulation models; Replicate and debug issues in pre-silicon environments; Collaborate with architects and developers to improve verification of complex features; Maintain and improve functional verification infrastructure and methodology; Document test plans and drive technical reviews
Seniority
Senior, hands-on IC
