ASIC Design Verification Engineer
Core
Develop leadership silicon technology for high throughput Ethernet products serving datacenter and cloud operators, focusing on PCIe and host interfaces.
Role type
Senior ASIC Design Verification Engineer
Builds
Next generation high performance Ethernet devices for AI and cloud mega data centers
Domain
Semiconductor / High-speed communication interfaces
Required skills
ASIC design process, RTL coding, simulation/verification, synthesis, timing closure, silicon validation, high-speed communication chip architecture, Python/Perl scripting
Preferred skills
Ethernet controller experience, PCIe experience
Technologies
PCIe, Ethernet, RTL, Python, Perl
Responsibilities
Conceive and develop leadership silicon technology, work with worldwide design and architecture team, define architecture, code RTL, perform simulation and verification, achieve timing closure, validate silicon
Seniority
Senior, hands-on IC
