Digital Design Verification Engineer
Core
Setting up UVM testbenches for large SoC designs, taking designs from specification through timing closure to physical design hand-off.
Role type
Digital Design Verification Engineer
Builds
Verification environments and testbenches for System-on-Chip (SoC) integration
Domain
Semiconductor / SoC Design Verification
Deliverable
production ML models
Required skills
UVM, SoC integration, testbench setup, design debug, timing closure, physical design hand-off
Technologies
UVM
Responsibilities
Operate with autonomy to take designs from specification to timing closure and physical design hand-off; Collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and meet milestones
Seniority
Mid-Senior, 5+ years experience
Sourced via workday · Listed on CareerPlan, which tracks 70,000+ jobs from 20+ sources.
