Memory Design Engineer
Core
Design and development of Single/Multiport SRAM and Register file compilers across 28nm to 5FF technologies.
Role type
Senior IC memory design engineer
Builds
High-speed, low-power memory compilers and SRAM blocks
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features
Required skills
High-speed/low-power CMOS circuit design, Memory compiler specification development, Split rail and power gating architecture, Silicon debug and failure analysis, Cadence/Mentor schematic and layout tools, Circuit simulation (HSPICE, HSIM, XARA, nWave), Timing analysis, Signal and Power integrity analysis
Preferred skills
Python/Perl/Scripting, Memory DFT knowledge
Technologies
28nm, 16FF, 7FF, 5FF, HSPICE, HSIM, XARA, nWave, Cadence, Mentor
Responsibilities
Circuit design and simulation of bitcells, decoders, and control logic; Develop critical path characterization flows; Perform statistical analysis for yield sign-off; Execute design tuning and margin analysis; Conduct logic simulations and timing analysis; Perform EM and IR drop analysis
Seniority
Senior, hands-on IC
