DFT Manager
Core
Manage and technically guide a high-performing DFT team focused on various ASIC engagements, defining chip-level testing plans and executing critical DFT tasks.
Role type
Senior IC DFT Manager
Builds
ASIC chip-level testing solutions and architectures
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, Scan design, MBIST, IO/IP test planning, ATE post-silicon debugging, yield improvement, cross-functional collaboration with physical design and verification teams
Preferred skills
Proficiency with Siemens Tessent, Synopsys TestMAX, SpyGlass DFT
Technologies
Siemens Tessent, Synopsys TestMAX, SpyGlass DFT
Responsibilities
Define chip-level testing plans including Scan, MBIST, and IO/IP tests; Collaborate with physical design, verification, and manufacturing teams on optimal DFT architectures; Execute DFT critical tasks; Work with Automated Test Equipment (ATE) post-silicon to achieve test coverage and improve manufacturing yield
Seniority
Senior, hands-on IC
