FPGA IP Software Development Engineer
Core
Design, develop, and validate high-performance FPGA Soft IP solutions from micro-architecture definition through physical hardware validation.
Role type
Senior RTL Design Engineer (FPGA IP)
Builds
FPGA Soft IP solutions for embedded systems
Domain
Semiconductor / FPGA Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL coding (System Verilog, Verilog, VHDL), FPGA tool flows (synthesis, P&R, STA), timing closure, CDC resolution, hardware bring-up/debug, Tcl/Python/Shell scripting
Preferred skills
Embedded SoC architectures (ARM Cortex, RISC-V), hardware-software co-design
Technologies
System Verilog, Verilog, VHDL, Quartus Prime, Vivado, Libero, Tcl, Python, Shell
Responsibilities
Define micro-architecture and implement reusable RTL code; Drive full FPGA tool flow including synthesis, place-and-route, and static timing analysis; Resolve complex multi-clock designs and timing violations; Develop testbenches and run behavioral simulations; Validate RTL functionality on evaluation boards using lab equipment; Collaborate with software and hardware teams on specifications and integration
Seniority
Senior, hands-on IC
