SOC Frontend Integration Engineer
Core
Constructing top-level System-on-Chip (SoC) RTL integration by assembling internal and third-party IPs into complex FPGA designs.
Role type
SoC Frontend Integration Engineer
Builds
Top-level SoC RTL designs for FPGA tapeout
Domain
Semiconductor / Hardware Design / FPGA
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design and integration (Verilog/SystemVerilog), SoC architecture knowledge, IP-based design methodologies, frontend quality checks (Lint, CDC/RDC), Linux environment proficiency, scripting (Perl/Python/Tcl/Shell), complex debugging
Preferred skills
AI/ML SoC knowledge
Technologies
Verilog, SystemVerilog, Quartus, Perl, Python, Tcl, Shell
Responsibilities
Construct SoC frontend RTL integration, own SoC top-level RTL hierarchy and connectivity strategy, drive SoC-level frontend quality checks and closure, partner with verification teams for simulation/emulation environments, collaborate with software teams for Quartus integration, debug complex integration issues across RTL and verification flows, review IP deliverables and influence interfaces/clocking/reset/power requirements, promote integration best practices, improve integration flows and automation
Seniority
Experienced IC Engineer
