Clocking Architect
Core
Define, design, and integrate clocking architectures for next-generation FPGA and SoC devices, ensuring robust clock delivery and compliance with timing requirements across high-speed protocols.
Role type
Senior IC Clocking Architect
Builds
Programmable logic devices (FPGA/SoC) for AI, cloud, networking, and edge markets
Domain
Semiconductor hardware design (FPGA/SoC) and high-speed digital interfaces
Deliverable
production ML models | product features
Required skills
Clock tree topology design, PLL/DLL resource allocation, SDC constraint authoring, PCIe clocking, High-Speed Memory I/O (DDR5, HBM), ARM subsystem clocking, SerDes clocking, Clock Domain Crossing (CDC) architecture, Timing closure, DVFS strategies
Preferred skills
Experience with Synopsys SpyGlass/Cadence JasperGold CDC tools, knowledge of AI accelerator clocking (systolic arrays, vector engines), mentorship of junior engineers
Technologies
PCIe Gen4/5/6, DDR5, LPDDR5, HBM2E/HBM3, ARM Cortex-A/M/R, eSPI, SPI, JTAG, LPC, Ethernet (1G-400G), SerDes, Synopsys PrimeTime, Cadence Tempus
Responsibilities
Own full-chip clocking strategy and topology; Define protocol-specific clocking for PCIe, Memory, ARM, Ethernet, and SerDes; Architect CDC solutions and verification; Author functional and DFT timing constraints; Lead cross-functional clocking reviews and sign-off
Seniority
Senior, hands-on IC
