ESD and LUP Engineer
Core
Lead Electro-Static Discharge (ESD) and Latch-Up (LUP) Prevention development for complex integrated circuits on advanced process nodes.
Role type
Senior IC reliability engineer (ESD/LUP)
Builds
Robust protection strategies for high-voltage and high-speed applications
Domain
Semiconductor manufacturing / Integrated Circuit design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Device physics, semiconductor reliability, high-voltage structure design, EDA tools (Calibre PERC, Ansys PathFinder), failure analysis, silicon validation
Preferred skills
Cross-functional collaboration, customer consultation
Technologies
Calibre PERC, Ansys PathFinder
Responsibilities
Design and implement protection circuits for ESD across diverse IC devices; Establish and refine ESD and LUP rules for new process nodes; Review customer specifications to determine optimal protection strategies; Direct and perform test procedures to verify protection schemes; Lead debugging and resolution of testing failures; Coordinate with CAD/Software teams to integrate ESD/LUP flows
Seniority
Senior, hands-on IC
