Digital Signal Processing and System Validation Engineer
Core
Designing digital signal processing blocks and validating ASIC architecture for next-generation optical data center connectivity products.
Role type
Senior IC digital signal processing and system validation engineer
Builds
High-speed optical data center networking ASICs (SerDes, serial links)
Domain
Semiconductor / High-speed data center networking / Optical interconnects
Deliverable
production ML models | product features
Required skills
Digital signal processing design, SerDes architecture, post-silicon validation, mixed-signal IP validation, ADC design, CDR and equalization architectures, Verilog-HDL/System Verilog coding, front-end simulation tools (NCVerilog, NCSIM, Simvision, Spyglass), DFT and RTL design, synthesis, CDC, static timing analysis, SDF annotated simulations, parasitic delay analysis
Preferred skills
High-speed DSP algorithms, FFE/DFE/CDR adaptation for PAM4 signals, logic optimization for low power and timing, Signal Integrity and Power Integrity modeling, Verilog AMS simulation, behavioral analog circuit modeling
Technologies
Matlab, Simulink, Verilog, System Verilog, NCVerilog, NCSIM, Simvision, Spyglass
Responsibilities
Design digital signal processing blocks for optical data center connectivity; validate ASIC architecture pre- and post-silicon; translate CDR and equalization architectures into Verilog code; perform synthesis, CDC, and static timing analysis; conduct SDF annotated simulations with parasitic delay analysis
Seniority
Senior, hands-on IC