Senior Debug Verification Engineer
Core
Design for Debug architecture verification for SoC, FPGA, and full chip designs, creating test cases and testbenches using UVM methodology.
Role type
Senior Debug Design Verification Engineer
Builds
Pre-silicon verification plans and testbenches for complex ASIC/FPGA designs
Domain
Semiconductor hardware verification (FPGA/ASIC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, formal verification, Linux/Unix scripting, Perl, Python, JTAG, High speed USB, PCIe based debug, ARM debug architecture, RISC debug architecture
Preferred skills
UltraSoC/Tessent Embedded Analytics Debug Architecture, Emulation
Technologies
UVM, SystemVerilog, Perl, Python, Linux, Unix, JTAG, USB, PCIe, ARM, RISC
Responsibilities
Create testcases and testbench with UVM methodology; Define verification strategies/methodology and test plan for fullchip/system functional verification; Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan; Perform pre-silicon system verification for SoC, FPGA & Full Chip design
Seniority
Senior, hands-on IC
