DDR Memory Interface System Validation Lead Engineer
Core
Drive validation, characterization, and debug activities for advanced DDR5 and LPDDR5 memory interfaces on next-generation FPGA devices.
Role type
Senior IC memory interface validation engineer
Builds
High-speed memory subsystems and FPGA platforms
Domain
Semiconductor / FPGA / High-speed memory interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DDR5/LPDDR5 memory subsystem validation, system-level validation environment development, pre/post-silicon functional and electrical validation, timing characterization, signal integrity analysis, complex silicon/firmware/board debugging, JEDEC compliance testing, high-speed protocol analyzer usage, validation automation framework development
Preferred skills
None stated
Technologies
DDR5, LPDDR5, FPGA, JEDEC specifications, protocol analyzers, oscilloscopes, logic analyzers, traffic generators
Responsibilities
Define and execute validation strategies for DDR5/LPDDR5 across multiple FPGA programs; Develop comprehensive system-level validation environments and test suites; Perform pre-silicon and post-silicon functional and electrical validation of controllers and PHYs; Analyze signal integrity and timing behavior including eye diagrams and jitter; Debug complex silicon, firmware, and board-level issues; Collaborate with board design teams on stack-up reviews, routing strategies, and memory topology optimization; Develop and maintain validation methodologies and automation frameworks.
Seniority
Senior, hands-on IC
