ASIC Verification Engineer
Core
Verify complex communication ASICs (PHYs) for high-speed interconnect products used in AI and data center networks.
Role type
ASIC Verification Engineer
Builds
Production-ready silicon for high-performance Ethernet PHYs
Domain
Semiconductor / High-Speed Interconnects / AI Infrastructure
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog, VHDL, IEEE Ethernet protocols, logic design, computer architecture, networking protocols
Preferred skills
C/C++, Object-Oriented Programming (OOP), Python, Perl, TCL scripting
Technologies
SystemVerilog UVM
Responsibilities
Design and maintain advanced verification environments and testbench components; Own verification at block and chip levels; Develop custom scripts and tools to improve verification efficiency; Collaborate with architecture, design, and firmware teams across the product lifecycle.
Seniority
Mid-level (3+ years experience) or New Grad
