R&D IC Design Engineer
Core
Architect block-level designs for high-speed (10Gbps to 400Gbps) backplane, cable, and optical fiber communication chips.
Role type
Senior IC Design Engineer (High-Speed Digital/ASIC)
Builds
ASIC chips for high-speed communication interfaces
Domain
Semiconductor / High-Speed Digital Circuit Design
Deliverable
production ML models | product features
Required skills
HDL coding (Verilog/VHDL), Static Timing Analysis (STA), Equivalency checking, CDC checks, RTL/Gate-level simulation, Silicon debugging, Scripting (Python/Perl/Unix), Low-power design, Design for Test (DFT), Design for Manufacturing (DFM), ARM subsystem knowledge, High-speed digital circuit design, 10G/100G Ethernet/OTN knowledge
Preferred skills
Digital Signal Processing (DSP), Error Correction Code (ECC), High-level Synthesis, Backplane/cable/optical fiber communication knowledge
Technologies
Verilog, VHDL, Python, Perl, Unix, ARM, Ethernet, OTN
Responsibilities
Architect block-level design specifications from marketing/system requirements; Prepare detailed design documents and timing constraint files; Perform design tradeoff analysis (power, area, schedule); Generate verification and test plans; Execute silicon bring-up and debugging.
Seniority
Senior, hands-on IC
