Staff RTL Design Engineer
Core
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
Role type
Staff CPU Microarchitect/RTL design engineer
Builds
RISC-V CPU cores and hardware IP
Domain
Semiconductor / CPU Design / RISC-V Architecture
Deliverable
production ML models | product features
Required skills
CPU RTL design, Verilog, System Verilog, VHDL, microarchitecture development, physical design optimization, performance modeling
Preferred skills
RISC-V architecture knowledge, Scala, Chisel, object-oriented programming, functional programming
Technologies
Verilog, System Verilog, VHDL, Scala, Chisel
Responsibilities
Architect and implement new features and ISA extensions in CPU core generators; develop microarchitecture specifications and documentation; create and execute verification test plans; collaborate with physical implementation teams to optimize frequency, area, and power; work with performance modeling teams for optimization.
Seniority
Staff, hands-on IC
