Staff Engineer Formal(IOMMU-N)
Core
Develop and implement formal verification plans for complex digital designs, primarily targeting RISC-V processors and other IP blocks designed in Chisel.
Role type
Staff Engineer, Formal Verification (Hardware)
Builds
RISC-V processor cores and custom IP blocks
Domain
Semiconductor / Chip Design / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Formal verification methodologies, Chisel hardware description language, Scala programming, Assertion-based verification, Model checking, Equivalence checking, TCL scripting, Digital design principles, Computer architecture, FPGA/ASIC design flows
Preferred skills
Constrained-random verification techniques, Functional coverage strategies, UVM methodology adaptation
Technologies
Chisel, Scala, TCL, chisel-formal, Formal traits, assert statements
Responsibilities
Develop and implement formal verification plans for complex digital designs; Write and debug formal properties (assertions and assumptions) in Chisel/Scala; Utilize formal verification tools to prove design correctness; Collaborate with design engineers to understand specifications and review architectures; Develop verification environments and infrastructure using Chisel, Scala, and TCL; Identify and implement strategies for improving formal verification efficiency and coverage; Analyze formal verification results and debug failures.
Seniority
Staff, hands-on IC
