Senior Design Verification Infrastructure Engineer - VIPs and Testbench
Core
Architect, develop, and maintain the Verification Platform (VIPs, AIPs, testbench components) for SiFive's RISC-V chip design verification.
Role type
Senior Design Verification Infrastructure Engineer
Builds
Reusable verification infrastructure, VIPs, AIPs, and testbenches for internal Design Verification teams
Domain
Semiconductor / RISC-V Chip Design / Design Verification
Deliverable
infrastructure
Required skills
Design Verification, SystemVerilog, UVM, VIP/AIP development, software engineering practices
Preferred skills
Chisel, Scala, Python, EDA tools, DevOps, CI/CD
Technologies
SystemVerilog, UVM, Chisel, Scala, Python
Responsibilities
Architect and maintain Verification Platform infrastructure; Develop libraries for verification intent in Scala/Chisel; Develop VIPs/AIPs in SystemVerilog/UVM; Create test plans and testbenches for component verification; Educate teams on best practices
Seniority
Senior, hands-on IC
