Staff Design Verification Engineer – Cache Verification
Core
Drive verification of cache and memory-subsystem functionality, focusing on cache coherency, ordering, correctness, and subsystem integration for RISC-V processors.
Role type
Staff individual-contributor design verification engineer
Builds
RISC-V compute platforms for AI, machine learning, automotive, data center, mobile, and consumer applications
Domain
Semiconductor chip design, computer architecture, memory hierarchy
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, cache architecture, memory hierarchy, cache coherency protocols, constrained-random verification, coverage analysis, debugging RTL and testbenches
Preferred skills
Multicore verification, performance-oriented verification, formal techniques, emulation/FPGA-assisted debug, Python/C/C++ scripting
Technologies
SystemVerilog, UVM, Python, C, C++
