Design Verification Engineer II – CPU Subsystem
Core
Drive verification of CPU subsystem functionality in high-performance core development, ensuring design intent is captured and risks are identified early.
Role type
Senior IC Design Verification Engineer (CPU Subsystem)
Builds
High-performance RISC-V CPU cores and subsystems for data-intensive applications
Domain
Semiconductor / Computer Architecture / CPU Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, CPU microarchitecture, verification planning, directed and constrained-random testing, failure analysis, functional coverage closure, Python/C++ scripting
Preferred skills
Out-of-order core verification, formal verification, emulation, mentoring, OOP principles
Technologies
SystemVerilog, UVM, Python, C/C++, RISC-V
Responsibilities
Own verification planning and execution for CPU subsystem areas; Develop scalable verification environments, checkers, and coverage models; Execute test scenarios to expose corner cases in pipeline and memory consistency; Drive failure analysis and root-cause debug; Contribute reusable verification methodology and automation; Partner across architecture, RTL, and software teams.
Seniority
Senior, hands-on IC
