Principal Design Verification Engineer – CPU Subsystem Power Management
Core
Lead verification of CPU-subsystem power-management functionality across complex SoC environments, ensuring data-center-grade quality and signoff readiness.
Role type
Principal Design Verification Engineer (CPU Subsystem Power Management)
Builds
CPU subsystems with advanced power management features for data center applications
Domain
Semiconductor / Chip Design / CPU Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, scalable verification planning, assertions, checkers, coverage strategy, Python scripting, root-cause debug, formal verification, emulation, power-aware verification
Preferred skills
PMC verification, live retention checkers, clock-domain interaction analysis, coherency-sensitive traffic verification, verification methodology definition
Technologies
SystemVerilog, Python, Formal Verification, Emulation, Simulation
Responsibilities
Lead verification planning and execution for power-management features from unit to subsystem level; Define verification strategies and closure criteria for power-state transitions and clock/reset sequencing; Drive verification across CoreIP, PMC, and uncore environments; Own high-value stress and corner-case scenarios for power-state sequencing and retention; Partner with architecture and RTL teams to reduce specification ambiguity; Drive efficient failure analysis and root-cause debug; Contribute reusable verification infrastructure; Mentor engineers on subsystem-level debug challenges; Define signoff expectations for data-center-grade CPU subsystems
Seniority
Principal, technical lead with mentorship
