Staff Design Verification Engineer – Coherent Interconnect (CHI)
Core
Drive verification of a next-generation cache-coherent interconnect (CHI) subsystem, focusing on protocol behavior, data movement, and subsystem integration.
Role type
Staff IC design verification engineer (coherent interconnect)
Builds
Coherent interconnect subsystems for high-performance compute platforms
Domain
Semiconductor / Chip Design / Computer Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, cache-coherent systems, memory subsystems, coherent protocols, protocol behavior (ordering, snooping, flow control), verification environment development, debugging, RTL analysis
Preferred skills
ARM CHI, large subsystem integration, memory consistency, formal verification, emulation-assisted debug, Python scripting, technical mentorship
Technologies
SystemVerilog, Python, RTL, Assertions, Scoreboards, Coverage Models
Responsibilities
Drive verification of CHI transactions across request, response, snoop, and data paths; Develop and maintain robust verification environments and coverage models; Verify integration behavior across caches, home nodes, and bridges; Define high-value directed and constrained-random scenarios; Partner with architecture and design teams to clarify requirements; Analyze failures and drive durable fixes; Improve verification methodology and infrastructure; Mentor other engineers.
Seniority
Staff, hands-on IC with technical leadership
