Senior RTL Design Engineer - CPU
Core
Designing industry-leading CPU cores based on the RISC-V architecture, focusing on microarchitecture, RTL implementation, and performance optimization.
Role type
Senior IC CPU Microarchitecture/RTL Design Engineer
Builds
High-performance RISC-V CPU cores and hardware IP
Domain
Semiconductor / CPU Design / RISC-V Architecture
Deliverable
production ML models | product features | infrastructure
Required skills
CPU RTL design, Verilog/System Verilog/VHDL, Chisel, functional programming, compiler infrastructure, data modeling, test-driven development
Preferred skills
Scala/Chisel, Bluespec, RISC-V architecture expertise, UVM/verification principles, Git/Github
Technologies
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, UVM, Git, Github, Jira, Confluence
Responsibilities
Architect and implement new features and ISA extensions in CPU core generators; Integrate design content into the Chisel/FIRRTL framework; Perform sandbox verification and collaborate on verification test plans; Work with physical implementation teams to optimize frequency, area, and power; Collaborate on performance modeling and optimization; Develop microarchitecture specifications and documentation
Seniority
Senior, hands-on IC
