Stage Ingénieur : Automatisation de la génération et de la maintenance de modèles AMS à l’aide de l’IA (F/H)
Core
Develop AI-assisted Python scripts and AI agents to automatically generate, migrate, and maintain Analog and Mixed-Signal (AMS) behavioral models for automotive integrated circuits.
Role type
Junior IC verification engineer (AMS modeling & AI automation)
Builds
Automated AMS model generation pipelines, a 'Golden Library' of reference models, and AI-driven migration tools.
Domain
Semiconductor verification / Automotive electronics / AI for EDA
Deliverable
production ML models
Required skills
Verilog-A, Verilog-AMS, SystemVerilog, Python, EDA tools (Cadence Virtuoso/Xcelium), circuit design (analog/digital), generative AI concepts
Preferred skills
Experience with generative AI tools, advanced EDA tool proficiency
Responsibilities
Develop AI-assisted Python scripts for automatic model migration; Build and enrich a 'Golden Library' of reference AMS models; Develop and experiment with AI agents to generate models from netlists; Validate generated models for quality and maintainability.
Seniority
Intern / Final year engineering student
