Principal CAD Engineer Digital Verification
Core
Build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development to improve verification productivity and debug efficiency.
Role type
Principal CAD Engineer (Digital Verification)
Builds
Regression systems, automation frameworks, and advanced verification methodologies (UVM, coverage, CI/CD flows)
Domain
Semiconductor / ASIC/SoC Design / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Digital verification flow expertise, System Verilog, UVM, scripting (Python/Tcl/Perl), Linux environments, EDA tool proficiency, regression/CI/CD system management, compute farm optimization, cross-functional collaboration
Preferred skills
AI/ML-based DV tools experience, cloud-based regression environments, automation of support workflows
Technologies
VCS, Xcelium, Verdi, vManager, Cadence, Synopsys, Siemens, Matlab, Coside, LSF
Responsibilities
Act as primary support interface for DV teams to troubleshoot simulation, regression, and debug flows; Deploy, integrate, and maintain CAD tools and environments; Collaborate with DV teams to identify bottlenecks and provide solutions; Work with EDA vendors to track, debug, and escalate tool issues; Monitor and optimize infrastructure usage (compute farms, LSF); Provide methodology guidance and training to verification engineers
Seniority
Principal, hands-on IC with strategy & mentorship
