Senior/Principal verification Engineer
Core
Define and execute comprehensive verification strategies for large System-on-Chip (SoC) designs, ensuring functional closure and quality through advanced verification methodologies.
Role type
Senior/Principal Verification Engineer (SoC)
Builds
Scalable SystemVerilog/UVM-based verification environments, reusable components, and end-to-end SoC verification flows.
Domain
Semiconductor hardware design, SoC verification, RTL design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random testing, assertion-based verification, formal verification collaboration, debug and root cause analysis, coverage modeling, SoC architecture knowledge
Preferred skills
Interconnect verification, cache coherency verification, memory subsystem verification, low-power verification, performance stress testing, leadership and mentoring
Technologies
SystemVerilog, UVM, SVA, third-party VIPs, custom verification IPs
Responsibilities
Define verification strategies and plans based on architecture; develop block-level and SoC-level verification environments; drive verification closure using coverage metrics; analyze simulation failures and resolve bugs; lead complex debug activities across multiple IPs; mentor junior and senior engineers on verification methodologies.
Seniority
Senior/Principal, hands-on IC with leadership responsibilities
