Lead Engineer - SoC Design Verification
Core
Design Verification Engineer responsible for executing complex SoC verification plans, developing UVM-based environments, and driving DV closure for ARM-based microcontrollers.
Role type
Senior IC SoC Design Verification Engineer
Builds
Production SoCs and IP blocks for embedded microcontroller applications
Domain
Semiconductor / Embedded Systems / SoC Design
Deliverable
production ML models | product features
Required skills
SoC-level verification, IP-level verification, UVM, SystemVerilog, Verilog, constrained-random verification, C-based DV, assertion-based verification (SVA), functional coverage analysis, regression test execution, RTL simulation, gate-level simulation, power-aware verification (UPF), EDA tool proficiency (Synopsys VCS, Cadence Xcelium)
Preferred skills
Low-power verification (UPF), gate-level simulation, power-aware simulation, multi-interface verification (SPI, I2C, UART, USB, PCIe, Ethernet, CAN, eSPI), Flash memory verification, security IP verification, Analog IP verification (ADC, DAC, PLLs)
Technologies
UVM, SystemVerilog, Verilog, C, Synopsys VCS, Cadence Xcelium, RTL, netlist, FPGA, Emulation platform
Responsibilities
Develop and own SoC-level and IP-level verification suites with coverage goals; Execute verification plans according to product specifications; Develop, debug, and run UVM-based verification environments; Define and develop test cases, stimulus, and assertions; Drive DV closure on diverse IPs and subsystems; Collaborate with design teams for issue resolution and sign-off; Mentor junior team members
Seniority
Senior, hands-on IC
