Internship - Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips
Core
Designing hardware-based robustness mechanisms to detect or correct bit errors on the SMI bus and within on-chip register files for automotive PHY chips.
Role type
Hardware Intern (Digital RTL Design)
Builds
Hardware IP blocks for error detection/correction in SMI interfaces
Domain
Automotive semiconductor / Digital hardware design
Deliverable
production ML models | product features | infrastructure
Required skills
Digital logic design, SystemVerilog, FSM design, Register-file architecture, Fault-injection verification, Coverage-driven testbench methodology
Preferred skills
EDA tools, Code review processes
Technologies
SystemVerilog, IEEE 802.3 Clause 22/45, SMI/MDIO
Responsibilities
Prototype hardware mechanisms for SMI bus error detection/correction, Develop fault-injection verification environments, Design digital RTL for register interfaces
Seniority
Intern
