Senior IP Verification Engineer
Core
Verify complex IPs including graphics pipelines, memory subsystems, and interconnects for global design teams.
Role type
Senior IC IP verification engineer
Builds
Scalable SystemVerilog/UVM-based verification environments with reusable components
Domain
Semiconductor hardware design (graphics, memory, interconnects)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog, functional verification methodologies, Assertions (SVA), coverage analysis, interconnect protocols (AXI, AHB, CHI, PCIE), RTL debugging
Preferred skills
Formal verification
Responsibilities
Develop and execute verification plans for memory controllers and interconnects, own end-to-end IP verification sign-off, manage regressions and debug failures, achieve high-quality functional and code coverage metrics
Seniority
Senior, hands-on IC
