Principal Physical Design Engineer
Core
Lead the back-end physical design competence for disruptive Non-Volatile Memory (NVM) IPs targeting automotive MCUs and MPUs.
Role type
Principal Physical Design Lead (NVM IP)
Builds
Scalable, production-ready NVM IP solutions (MRAM/RRAM) in FinFET technology nodes.
Domain
Semiconductor / Non-Volatile Memory / Automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Place and Route design, RTL2GDS flow execution, Physical Verification, Flow automation scripting, Analog-Mixed signals design, FinFET node expertise
Preferred skills
NVM technology knowledge, Macro architecture expertise, Flexibility between Cadence and Synopsys toolsets
Technologies
Cadence, Synopsys
Responsibilities
Lead RTL2GDS flow (Synthesis, Floor-Planning, CTS, P&R, ECO, Chip Finishing), Run Physical Verification, Develop automated physical design flows using AI tools, Mentor junior engineers
Seniority
Principal, hands-on IC with mentorship
