Junior Layout Engineer
Core
Delivering floorplan activities, analog layout blocks, and physical verifications for high-performance microcontrollers and analog custom products.
Role type
Junior IC analog layout engineer
Builds
High-performance microcontrollers (MCUs) and analog custom products for industrial automation and autonomous home applications
Domain
Semiconductor design, analog IC, physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, device physics, IC ESD protection strategies, floorplan strategies, DRC/LVS/DFM, parasitic extraction, Cadence Virtuoso, Mentor Graphics Calibre
Preferred skills
Technical training, writing technical guidelines, cross-functional collaboration
Technologies
Cadence Virtuoso, Mentor Graphics Calibre
Responsibilities
Delivering floorplan activities at IP level, participating in power supply strategy and signal distribution, delivering analog layout blocks, running physical verifications (DRC/LVS/DFM/parasitic extraction), participating in design reviews and documentation, ensuring design for quality and reliability
Seniority
Junior, 0-2 years experience
