Sr. Analog Validation Engineer
Core
Comprehensive validation of key product indicators (KPIs) for all analog circuitry in a platform, ensuring instrumentation and automation are prepared for silicon testing.
Role type
Senior IC Analog Validation Engineer / Architect
Builds
Automated parametric validation plans, test scripts, and hardware measurement sequences
Domain
Semiconductor / Analog Circuit Design / High-Speed/RF
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Parametric validation planning, DUT configuration software, hardware automation sequencing, PVT analysis, hardware debugging, schematic reading, SerDes validation, Ethernet IEEE 802.3 protocols
Preferred skills
C programming, TestStand, Python, Data analysis (Excel, JMP, PowerBI), AI prompting for software generation
Technologies
Oscilloscopes, BER testers, vector network analyzers, phase noise analyzers, SerDes, Ethernet IEEE 802.3
Responsibilities
Build parametric validation plans from electrical specifications; Write software to configure device under test (DUT); Create hardware automation sequences for parametric measurements; Analyze parametric data to report pass/fail/margin; Interface with cross-functional teams to debug IP-related issues; Research and recommend required measurement hardware; Generate hardware design requirements and participate in schematic/layout reviews
Seniority
Senior, hands-on IC