<Data Center> Datacenter Compute SoC Performance Modeling Architect
Core
Develop and maintain high-speed, cycle-accurate, and transaction-level architectural simulators to evaluate design trade-offs and project system performance for next-generation cloud and datacenter processors.
Role type
Senior IC performance modeling architect
Builds
High-fidelity architectural simulators for multi-core datacenter SoCs
Domain
Semiconductor design / Datacenter compute
Deliverable
production ML models
Required skills
C++, SystemC, multi-core SoC architecture, NoC design, PCIe/CXL protocols, workload characterization, Python, data analysis
Preferred skills
RTL verification, post-silicon validation, performance bottleneck analysis
Technologies
C++, SystemC, Python
Responsibilities
Design and maintain cycle-accurate and transaction-level performance models for multi-core datacenter SoCs; Analyze and characterize cloud-native workloads, microservices, databases, and AI/ML data processing pipelines; Conduct what-if analyses and architectural design sweeps to optimize cache sizes, memory bandwidth, latency, interconnect topologies, and core counts; Identify micro-architectural and system-level performance bottlenecks and propose innovative hardware or software solutions; Work with RTL verification and post-silicon validation teams to correlate the performance model against RTL simulations, emulators, and actual silicon; Build and enhance tracing tools, data visualization dashboards, and automated performance regression pipelines using Python and data analysis libraries.
