Senior Digital Design Engineer
Core
Design and optimize digital hardware platforms for 4/5/6G modems, focusing on PPA (Power, Performance, Area) and subsystem integration.
Role type
Senior Digital Design Engineer (Hardware IP)
Builds
4/5/6G modem hardware platforms and digital IP subsystems
Domain
Telecommunications / Semiconductor / 5G/6G
Required skills
RTL design, timing closure, digital IP architecture, clock and bus design (AXI/APB/NOC), async design, high-speed interface design, PPA optimization, gate-level integration
Technologies
RTL, AXI, APB, NOC
Responsibilities
Define hardware architecture of digital IP/systems including clock, bus, async design, and high-speed interfaces; Perform subsystem integration from RTL to gate level including timing closure and testability; Optimize PPA for 4/5/6G modem hardware platforms; Improve design methodology and integration flows
Seniority
Senior, hands-on IC
