Senior Manager IP Design
Core
Leading a design team in India to develop critical IP circuits for all DRAM-related memory products.
Role type
Senior Manager, IP Design
Builds
Analog and digital IP circuits for DRAM memory products
Domain
Semiconductor / Memory Storage / Analog & Digital CMOS Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog and digital CMOS design, circuit verification and optimization, layout verification, parasitic extraction, team leadership, device physics understanding, power network analysis
Preferred skills
DRAM circuit design, DRAM array knowledge, basic CMOS processing techniques, UNIX and Cadence design environment proficiency, Finesim and/or HSpice knowledge
Technologies
Cadence, UNIX, Finesim, HSpice
Responsibilities
Lead IP circuit design group, guide team on analog and digital IP circuits, verify silicon performance vs simulation, work with Product Engineering, collaborate with Process integration and transistor modeling personnel
Seniority
Senior, hands-on IC
