SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Core
Designing custom analog blocks for high-speed interface innovations, focusing on clocking architecture and signal chain optimization for memory and storage solutions.
Role type
Principal Analog Design Engineer (Mixed-Signal PHY)
Builds
High-speed interface circuits (clocking, transmitter, receiver) for next-generation memory and storage products.
Domain
Semiconductor / High-Speed SerDes / Memory & Storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal IC design, Clocking circuit design (PLL/DLL/CDR), Transistor-level simulation (HSpice), Jitter analysis, Analog-digital interface definition, Layout collaboration, Post-silicon characterization
Preferred skills
High-speed transmitter/receiver design, Die-to-die PHY architectures (UCIe/AIB), OTP/fuse calibration, Real-number modeling (RNM), Mixed-signal behavioral modeling
Technologies
HSpice, Verilog-AMS, UCIe, AIB, BoW
Responsibilities
Design custom analog blocks from spec to layout, Define PHY analog architecture, Develop transistor-level simulation testbenches, Define analog-digital interface specifications, Collaborate on analog layout review, Support post-silicon characterization and root cause analysis
Seniority
Principal, hands-on IC with strategy & mentorship