Senior Engineer - HBM Circuit Verification
Core
Designing and analyzing digital and analog circuits for memory products, specifically focusing on HBM circuit verification and timing closure.
Role type
Staff Verification Circuit Engineer
Builds
High-performance memory solutions (DRAM, NAND, NOR) for data centers, AI, and mobile applications
Domain
Semiconductor / Memory Storage / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
HBM circuit verification, SPICE simulation (DC/transient), Verilog MOS switch level models, Static Timing Analysis (STA), System Verilog Assertions, Gate level simulation with SDF back annotation, Latch based design timing analysis, Root cause debugging at gate/transistor level
Preferred skills
UVM
Technologies
SPICE, Verilog, System Verilog, SDF, UVM
Responsibilities
Write constraints and perform timing closure for core die STA; Develop and analyze building block and memory schematics; Debug gate level simulation failures and correlate with SPICE; Specify expected design behavior using System Verilog Assertions; Perform what-if analysis to validate circuit fixes
Seniority
Staff, hands-on IC